1. Field of the Invention
The present invention relates to a semiconductor arithmetic apparatus, and in particular, relates to a system which is capable of executing calculations such as image processing and the like at high speed.
2. Description of the Related Art
In concert with the development of informational equipment and the rapid spread of information networks such as the LAN and WAN which comprise the Internet in recent years, it has become possible to gain access to home pages installed in computers around the world and to display various types of image data on home terminals, and thus to easily acquire desired information. However, it is presently the case that almost all these images are static images, and in order to display moving image data, it is necessary to download such data over a longer period of time than that required for display of the images. This is because moving image data involves an amount of data which is very large with respect to the transmission capacity of the information network. For example, for a moving color image with a resolution of 640.times.480, if 30 frames a second are required for display, the data must be transmitted at approximately 220 Mbps. However, networks having such a large transmission capacity are not common. Accordingly, in order to transmit moving image data involving a large amount of data to a distant place, techniques are necessary for conducting data compression in real time in accordance with the transmission capacity of the communication circuits.
One method of data compression is termed vector quantization. In vector quantization, a freely selected vector having a certain number of dimensions is compared with a number of differing vectors having the same number of dimensions which were prepared in advance (a code book), and the most similar vector is selected from among these, and the original vector is quantized in accordance with the pattern number thereof. If the number of vectors within the code book (the code vectors) is smaller than the number of possible cases of the original vector, the data are compressed. During expansion, it is then only necessary to retrieve the vector corresponding to the number from the code book. For this reason, vector quantization has been widely known as a data compression algorithm which greatly simplifies expansion.
However, since the most similar vector must be selected from among a large a number of code book vectors, it is necessary to conduct an extremely large number of calculations during compression, and this causes a problem in that the processing takes a long period of time. In the vector quantization which is commonly employed in image data compression, a 4.times.4 pixel block is extracted from the two dimensional array of the image, and this is employed as a 16-dimension vector. If this vector is, for example, quantized using a CISC processor and 2,048 code book vectors, approximately 1,200,000 operations are required. Even if these operations are carried out using a 166 MHz Pentium processor (made by Intel), this is an enormous amount of calculation which will require approximately 20 seconds.
In order to solve this problem, a dedicated processor was developed which executes operations in parallel. Correlators which conduct a comparison between quantized vectors and code vectors and express the degree of similarity therebetween as numerical values are commonly disposed in parallel in such dedicated processors; the degree of similarity with respect to all code vectors is thus simultaneously calculated in a parallel manner. The distance between vectors is commonly employed in the calculation of the degree of similarity; the vector having the smallest distance is thus judged to have the largest degree of similarity. Accordingly, by providing a circuit which simultaneously accepts the distance data from the correlators in a parallel manner and finds the minimum value thereof, it is possible to carry out vector quantization at high speed.
However, in the structure of such minimum value detecting circuits, there is a problem in that once the processor has been produced, the number of code vectors is limited by the number of correlator blocks provided within the processor, and this is, at a maximum, on the level of 256. In particular, this is a factor hindering attempts to take advantage of the fact that as the number of code vectors increases, the quality of the image resulting after vector quantization has been carried out and compression and expansion have been performed is improved, and to appropriately select the number of code vectors in correspondence with the capacity of various communication lines. Furthermore, when the distance data from all code vectors are inputted in a batch manner and the minimum value is calculated, there is a problem in that as a result of the wiring delay within the processor, timing lags are likely to occur in the distance data outputted from each correlator, and the design thus becomes difficult.